Integrated circuits such as processors and memory devices typically communicate with each other using digital data signals and clock signals. Clock signals and data signals are typically “timed” or “phase aligned” with respect to each other, so that the clock signals can be used to latch the data.
FIG. 1 shows a prior art circuit to align a transmitted data signal with a received clock signal. The circuit includes clock buffer 102, divider 108, phase comparator 114, dummy clock buffer 118, delay lines 104 and 110, shift register 116, output buffer 106, and dummy output buffer 112.
The output data DQ is timed by the clock signal generated by delay line 104, which is controlled in parallel with delay line 110 by shift register 116. A delay-locked loop (DLL) circuit is formed by phase comparator 114, shift register 116, delay line 110, dummy output buffer 112, and dummy clock buffer 118. The delay of dummy output buffer 112 matches that of output buffer 106, and the delay of dummy clock buffer 118 matches that of clock buffer 102. By using matching delay circuits in the DLL, the phase of the signal on node 117 closely matches CLK, and the phase of DQ also closely matches CLK.